1. Field of the Invention
The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages each capable of receiving a plurality of words, a buffer memory and a sequencer for executing an instruction for saving, in a target page of the Flash memory, a series of external words received at an input terminal of the memory, by first of all saving the series of external words in the buffer memory.
2. Description of the Related Art
This Flash memory is particularly described in European patent application EP 1 111 621 and is marketed by the applicant under various product references.
As explained in the above-mentioned patent application, conventional Flash memories have the disadvantage that the number of memory cells that can be programmed simultaneously is low, due to the high programming current that the programming of each memory cell, by injection of hot electrons, requires. Thus, the number of binary words that can be simultaneously saved in a Flash memory is low, and much lower than the number of words that one page of the memory can receive. For a better understanding, the number of binary words that can be saved simultaneously in a Flash memory is generally one to two words of 8 bits each (bytes), i.e., 8 or 16 memory cells programmed simultaneously, while one page can classically receive 256 words.
Providing a buffer memory makes it possible to simulate a page-programming mode, by saving on the fly, in the buffer memory, a series of words received, and by subsequently programming the Flash memory, in a manner transparent to the user.
FIG. 1 schematically represents the architecture of a memory SFMEM1 of the type indicated above.
The memory SFMEM1 is here a serial Flash memory comprising a serial input/output terminal IO, an input interface circuit ICT, an output interface circuit OCT, a parallel data bus DB, a micro-programmed sequencer SEQ1, a buffer memory BMEM1, a central Flash-type memory FMEM1 that is sector-erasable and word-programmable, a page address register PREG and a word address register WREG. The terminal IO is connected to the input of the circuit ICT and to the output of the circuit OCT. The register WREG is connected at input to the bus DB and its output is connected to an address input of the memory FMEM1 (least significant bits of the address input) as well as to an address input of the buffer memory BMEM1. The register PREG is connected at input to the bus DB and its output is connected to the address input of the memory FMEM1 (most significant bits of the address input). The buffer memory BMEM1 comprises a data input/output DIO connected to the bus DB. The memory FMEM1 comprises a data input DIN connected to the input/output DIO of the buffer memory and a data output DOUT connected to the input of the interface circuit OCT.
The circuit ICT transforms serial data received at the terminal IO into parallel data applied to the bus DB, while the circuit OCT transforms parallel data read in the memory FMEM1 into serial data applied to the terminal IO. The incoming data comprise command codes (read, write), addresses, and words to be saved in the Flash memory.
An operation of writing a series of words in a determined page, or target page, of the central memory FMEM1, is obtained by applying to the memory a command for erasing the sector in which the target page is located, then a command for writing the series of words that is, for example, in the following form:[CCPWRITE][PAD0][WAD0][W0][W1] . . . [Wn]and comprises a page write command code CCPWRITE, the address PAD0 of the target page Pi, the address WAD0, in the target page Pi, of the first word W0 to be saved, the first word to be saved W0 and the following words W1 . . . Wn.
The write command is executed by the sequencer SEQ1, which controls the various elements of the memory. The page address PAD is loaded into the register PREG and is applied to the address input of the memory FMEM1. The word address WAD is loaded into the register WREG and is applied to the address input of the Flash memory FMEM1 and to an address input of the buffer memory BMEM1. The words received W0 to Wn are saved one after the other in the buffer memory BMEM1, while incrementing the word address WAD every time. The time for saving in the buffer memory is short and everything happens for the user as if the series of words were being loaded into the programming latches of a page-programmable memory. The words are then transferred one after the other (or by group of two) into the target page of the memory FMEM1, in a series of programming steps controlled by the sequencer which involve the programming latches and are transparent to the user.
This Flash memory simulating the page mode provides possibilities of use that are similar to those offered by page-programmable EEPROM memories.
However, generally speaking, a page-programmable EEPROM memory is also word-programmable, since each group of memory cells forming a word in this memory can be individually erase-selected by means of a gate control transistor. Therefore, when a word or a group of words must be saved in an EEPROM memory, only the memory cells corresponding to this word or to this group of words are erased.
Conversely, in the Flash memory described above, the page is erased before saving the words present in the buffer memory, and all the data present in the page are lost.
Thus, before applying a command to the Flash memory for saving a series of words, the user must perform a complete read of the sector to insert the series of words to be changed into it, then re-save the entire sector page by page.